
85
8008H–AVR–04/11
ATtiny48/88
Figure 11-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O/8)
Figure 11-8 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode where OCR0A
is TOP.
Figure 11-8. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O/8)
11.8
8-bit Timer/Counter Register Description
11.8.1
TCCR0A – Timer/Counter Control Register A
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 3 – CTC0: Clear Timer on Compare Match Mode
This bit control the counting sequence of the counter, the source for maximum (TOP) counter
value, see
Table 11-2. Modes of operation supported by the Timer/Counter unit are: Normal
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3
2
1
0
–
CTC0
CS02
CS01
CS00
TCCR0A
Read/Write
R
R/W
Initial Value
0